The disclosure relates to methods for identifying at least one failure indicating scan test cell of an integrated circuit-under-test (CUT) and to a computer program product for performing such method.
Failure diagnosis may play an important role for example to ramp up yields during an integrated circuit manufacturing process. Limited observability due to test response compaction may negatively affect the diagnosis procedure. In particular, in compactor architectures with a low or very low number of outputs, for example only one output, observability may be strongly limited.
When a logic circuit fails at a test, fault diagnosis is for example used to narrow down possible locations of a defect. Fault diagnosis of scan designs with compactors are for example performed in two steps. In the first step, failures are mapped back through the compactor to the scan test cells of the CUT. In the second step, scan based fault diagnosis may be performed based on results from the first step.
Existing approaches may for example require iterations between the first step of mapping and the second step of scan based fault diagnosis. This may reduce for example time efficiency of the procedure. Furthermore, existing approaches may suffer from a limited effectivity and/or a reduced reliability of the results from the mapping.
Therefore, it is desirable to provide an improved concept for identifying failure indicating scan test cells of a CUT that allows for an improved reliability, effectivity and/or a reduced time requirement.